Secure and Low-Area Implementation of the AES Using FPGA

Hajisoltani, Muhamadali; Salarifard, Raziyeh; Soleimany, Hadi

doi:10.22042/isecure.2022.14.3.0

Secure and Low-Area Implementation of the AES Using FPGA

Document Type : Research Article

Authors

Muhamadali Hajisoltani ¹

Raziyeh Salarifard ²

Hadi Soleimany ¹

¹ Cyberspace Research Institue, Shahid Beheshti University, Tehran, Iran.

² Faculty of Computer Science and Engineering, Shahid Beheshti University, Tehran, Iran.

https://doi.org/10.22042/isecure.2022.14.3.0

Abstract

Masking techniques are used to protect the hardware implementation of cryptographic algorithms against side-channel attacks. Reconfigurable hardware, such as FPGA, is an ideal target for the secure implementation of cryptographic algorithms. Due to the restricted resources available to the reconfigurable hardware, efficient secure implementation is crucial in an FPGA. In this paper, a two-share threshold technique for the implementation of AES is proposed. In continuation of the work presented by Shahmirzadi et al. at CHES 2021, we employ built-in Block RAMs (BRAMs) to store component functions. Storing several component functions in a single BRAM may jeopardize the security of the implementation. In this paper, we describe a sophisticated method for storing two separate component functions on a single BRAM to reduce area complexity while retaining security. Out design is well suited for FPGAs, which support both encryption and decryption. Our synthesis results demonstrate that the number of BRAMs used is reduced by 50% without affecting the time or area complexities.

Keywords

Side-Channel Attacks

FPGA

Threshold Implementation

AES

20.1001.1.20082045.2022.14.3.10.4

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