Rashidi, B., Rezaeian Farashahi, R., Sayedi, S. (2015). Efficient implementation of low time complexity and pipelined bit-parallel polynomial basis multiplier over binary finite fields. The ISC International Journal of Information Security, 7(2), 101-114. doi: 10.22042/isecure.2016.7.2.3

B. Rashidi; R. Rezaeian Farashahi; S. M. Sayedi. "Efficient implementation of low time complexity and pipelined bit-parallel polynomial basis multiplier over binary finite fields". The ISC International Journal of Information Security, 7, 2, 2015, 101-114. doi: 10.22042/isecure.2016.7.2.3

Rashidi, B., Rezaeian Farashahi, R., Sayedi, S. (2015). 'Efficient implementation of low time complexity and pipelined bit-parallel polynomial basis multiplier over binary finite fields', The ISC International Journal of Information Security, 7(2), pp. 101-114. doi: 10.22042/isecure.2016.7.2.3

Rashidi, B., Rezaeian Farashahi, R., Sayedi, S. Efficient implementation of low time complexity and pipelined bit-parallel polynomial basis multiplier over binary finite fields. The ISC International Journal of Information Security, 2015; 7(2): 101-114. doi: 10.22042/isecure.2016.7.2.3

Efficient implementation of low time complexity and pipelined bit-parallel polynomial basis multiplier over binary finite fields

^{1}Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran

^{2}Department of Mathematical Sciences, Isfahan University of Technology, Isfahan, Iran

^{3}School of Mathematics, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran

Abstract

This paper presents two efficient implementations of fast and pipelined bit-parallel polynomial basis multipliers over GF (2^{m}) by irreducible pentanomials and trinomials. The architecture of the first multiplier is based on a parallel and independent computation of powers of the polynomial variable. In the second structure only even powers of the polynomial variable are used. The parallel computation provides regular and low-cost structure with low critical path delay. In addition, the pipelining technique is applied to the proposed structures to shorten the critical path and to perform the computation in two clock cycles. The implementations of the proposed methods over the binary extension fields GF (2^{163}) and GF (2^{233}) have been successfully verified and synthesized using Xilinx ISE 11 by Virtex-4, XC4VLX200 FPGA.

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