Security-aware register placement to hinder malicious hardware updating and improve Trojan detectability




Nowadays, bulk of the designers prefer to outsource some parts of their design and fabrication process to the third-part companies due to the reliability problems, manufacturing cost and time-to-market limitations. In this situation, there are a lot of opportunities for malicious alterations by the off-shore companies. In this paper, we proposed a new placement algorithm that hinders the hardware Trojan insertion or simplifies the detection process in existence of Trojans. Experimental results show that the proposed placement improves the Trojan detectability of the attempted benchmarks against Trojan insertion more than 20% in reasonable cost in delay and wire length.


 [1] S. Adee, "The Hunt for the Kill Switch, "In IEEE Spectrum, vol. 45, no. 5, 2008, pp. 34-39

[2] S. Jha and S.K. Jha, "Randomization Based Probabilistic Approach to Detect Trojan Circuit," Proceedings 11th IEEE High Assurance Systems Engineering Symposium, 2008, pp. 117-124.

[3] F. Wolff, C. Papachristou, S. Bhunia and R. Chakraborty, "Towards Trojan Free Trusted ICs: Problem Analysis and Detection Scheme, "In Proceedings Design, Automation and Test in Europe Conf., 2008, pp. 1362-1365.

[4] M. Banga and M. Hsiao, "A Region Based Approach for the Identification of Hardware Trojans, "In Proceedings IEEE International Workshop Hardware-Oriented Security and Trust, 2008, pp. 40-47.

[5] M. Banga and M. Hsiao, "A Novel Sustained Vector Technique for the Detection of Hardware Trojans," Proceedings 22nd International Conf. VLSI Design, 2009, pp. 327-332.

[6] D. Agrawal, S. Baktir, D. Karakoyunlu, P. Rohatgi and B. Sunar, "Trojan Detection Using IC Fingerprinting, "In Proceedings IEEE Symposium Security and Privacy, 2007, pp. 296-310.

[7] X. Wang, H. Salmani, M. Tehranipoor and J. Plusquellic, "Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis, "In Proceedings IEEE International Symposium Defect and Fault Tolerance of VLSI Systems, 2008, pp. 87-95.

[8] R. Rad, X.Wang, M. Tehranipoor and J. Plusquellic, "Power Supply Signal Calibration Techniques for Improving Detection Resolution to Hardware Trojans," In Proceedings IEEE/ACM International Conference Computer-Aided Design, 2008, pp. 632-639.

[9] J. Li and J. Lach, "At-Speed Delay Characterization for IC Authentication and Trojan Horse Detection," In Proceedings IEEE International Workshop Hardware-Oriented Security and Trust, 2008, pp. 8-14.

[10] Y. Jin, N. Kupp and Y. Markis, "DFTT: design for Trojan test," In Proceedings IEEE International Conference on Electronics, Circuits, and Systems, 2010, pp. 1681-1171

[11] H. Salmani, M. Tehranipoor, and J. Plusquellic, "Layout-aware scan-cell re-ordering for improving localized switching to detect hardware Trojans," In Journal of Low Power Electronics (JOLPE), 2012

[12] M. Potkonjak, "Synthesis of Trustable ICs using Untrusted CAD Tools," In Design Automation Conference, 2010, pp. 633-634.

[13] M. Tehranipoor and F. Koushanfar, "A Survey of Hardware Trojan Taxonomy and Detection," In IEEE Design & Test of Computer, 2010, pp. 10-25.

[14] X. Wang, M. Tehranipoor, and J. Plusquellic, "Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions," In Proceedings IEEE International Workshop Hardware-Oriented Security and Trust, 2008, pp. 15-19.

[15] S. K. Lim, "Practical problems in VLSI physical design automation," In Springer Pub., 2008.

[16] P. Banerjee, M.H. Jones and J.S. Sargent, "Parallel simulated annealing algorithm for cell placement on hypercube multiprocessors," In In IEEE Transactions on parallel and distributed systems, 1990, Vol. I, No. 1.

[17] J. A. Chandy, S. Kim, B. Ramkumar, S. Parkes, and P. Banerjee, "An evaluation of parallel simulated annealing strategies with application to standard cell placement," In In International Parallel Processing Symposium and International Conference on VLSI Design, 1996.

[18] S. Amanollahi and A. Jahanian, "EduCAD: an efficient, flexible and easily revisable physical design tool for educational purpose," In Design, Automation and Test in Europe, University booth, 2011.

[19] IWLS 2005 Benchmarks, Available on, 2005.

[20] J. Cong and C. Koh, "Minimum-Cost Bounded-Skew Clock Routing," In Proceedings IEEE International Symposium on Circuits and Systems, 1995, pp. 215-218.