Secure FPGA Design by Filling Unused Spaces



1 computer department of Isfahan university

2 Iran- Tehran


Nowadays there are different kinds of attacks on Field Programmable Gate Array (FPGA). As FPGAs are used in many different applications, its security becomes an important concern, especially in Internet of Things (IoT) applications. Hardware Trojan Horse (HTH) insertion is one of the major security threats that can be implemented in unused space of the FPGA. This unused space is unavoidable to meet the place and route requirements. In this paper, we introduce an efficient method to fill this space and thus to leave no free space for inserting HTHs. Using a shift register in combination with gate-chain is the best way of filling unused space, which incurs a no increase in power consumption of the main design. Experimental results of implementing a set of IWLS benchmarks on Xilinx Virtex devices show that the proposed prevention and detection scheme imposes a no power overhead with no degradation to performance and critical path delay of the main design


[1] R. Karam, T. Hoque, S. Ray, M. Tehranipoor, and S. Bhunia, “Mutarch: Architectural diversity for fpga device and ip security,” in Design Automation Conference (ASP-DAC), 2017 22nd Asia and South Pacific, 2017, pp. 611-616: IEEE.

[2] S. Mal-Sarkar, A. Krishna, A. Ghosh, and S. Bhunia, “Hardware trojan attacks in fpga devices: threat analysis and effective counter measures,” in Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI, 2014, pp. 287-292: ACM.

[3] S. M. Trimberger and J. J. Moore, “FPGA security: Motivations, features, and applications,” Proceedings of the IEEE, vol. 102, no. 8, pp. 1248- 1265, 2014.

[4] R. S. Chakraborty, I. Saha, A. Palchaudhuri, and G. K. Naik, “Hardware Trojan insertion by direct modification of FPGA configuration bitstream,” IEEE Design & Test, vol. 30, no. 2, pp. 45-54, 2013.

[5] J. Li and J. Lach, “At-speed delay characterization for IC authentication and Trojan horse detection,” in Hardware-Oriented Security and Trust, 2008. HOST 2008. IEEE International Workshop on, 2008, pp. 8-14: IEEE.

[6] S. Zamanzadeh and A. Jahanian, “ASIC design protection against reverse engineering during the fabrication process using automatic netlist obfuscation design flow,” The ISC International Journal of Information Security, vol. 8, no. 2, pp. 93-104, 2016.

[7] M. Lecomte, J. Fournier, and P. Maurine, “An onchip technique to detect hardware Trojans and assist counterfeit identification,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 12, pp. 3317-3330, 2017. [8] M. Banga and M. S. Hsiao, “A novel sustained vector technique for the detection of hardware Trojans,” in VLSI Design, 2009 22nd International Conference on, 2009, pp. 327-332: IEEE.

[9] M. S. Samimi, E. Aerabi, Z. Kazemi, M. Fazeli, and A. Patooghy, “Hardware enlightening: No where to hide your hardware trojans!,” in OnLine Testing and Robust System Design (IOLTS), 2016 IEEE 22nd International Symposium on, 2016, pp. 251-256: IEEE.

[10] J. He, Y. Zhao, X. Guo, and Y. Jin, “Hardware trojan detection through chip-free electromagnetic side-channel statistical analysis,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 10, pp. 2939-2948, 2017.

[11] S. Zamanzadeh and A. Jahanian, “Security Path: An Emerging Design Methodology to Protect the FPGA IPs Against Passive/Active Design Tampering,” Journal of Electronic Testing, vol. 32, no. 3, pp. 329-343, 2016.

[12] M. Tehranipoor and C. Wang, Introduction to hardware security and trust. Springer Science & Business Media, 2011. [13] F. Courbon, P. Loubet-Moundi, J. J. Fournier, and A. Tria, “A high efficiency hardware trojan detection technique based on fast SEM imaging,” in Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015, pp. 788-793: EDA Consortium.

[14] S. Mal-Sarkar, R. Karam, S. Narasimhan, A. Ghosh, A. Krishna, and S. Bhunia, “Design and validation for FPGa trust under hardware Trojan attacks,” IEEE Transactions on Multi-Scale Computing Systems, vol. 2, no. 3, pp. 186-198, 2016. [15] M.-L. Flottes, S. Dupuis, P.-S. Ba, and B. Rouzeyre, “On the limitations of logic testing for detecting hardware Trojans horses,” in Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015 10th International Conference on, 2015, pp. 1-5: IEEE.

[16] S. Bhunia, M. S. Hsiao, M. Banga, and S. Narasimhan, “Hardware Trojan attacks: threat analysis and countermeasures,” Proceedings of the IEEE, vol. 102, no. 8, pp. 1229-1247, 2014.

[17] P. Kitsos and A. G. Voyiatzis, “FPGA Trojan detection using length-optimized ring oscillators,” in Digital System Design (DSD), 2014 17th Euromicro Conference on, 2014, pp. 675-678: IEEE.

[18] K. Xiao and M. Tehranipoor, “BISA: Built-in selfauthentication for preventing hardware Trojan insertion,” in Hardware-Oriented Security and Trust (HOST), 2013 IEEE International Symposium on, 2013, pp. 45-50: IEEE.

[19] P.-S. Ba, M. Palanichamy, S. Dupuis, M.-L. Flottes, G. Di Natale, and B. Rouzeyre, “Hardware trojan prevention using layout-level design approach,” in Circuit Theory and Design (ECCTD), 2015 European Conference on, 2015, pp. 1-4: IEEE. [20] A. Amelian and S. E. Borujeni, “A Side-Channel Analysis for Hardware Trojan Detection Based on Path Delay Measurement,” Journal of Circuits, Systems and Computers, vol. 27, no. 09, p. 1850138, 2018.

[21] B. Khaleghi, A. Ahari, H. Asadi, and S. BayatSarmadi, “Fpga-based protection scheme against hardware trojan horse insertion using dummy logic,” IEEE Embedded Systems Letters, vol. 7, no. 2, pp. 46-50, 2015.

[22] H. Yu, H. Lee, S. Lee, Y. Kim, and H.-M. Lee, “Recent Advances in FPGA Reverse Engineering,” Electronics, vol. 7, no. 10, p. 246, 2018.

[23] J.-B. Note and . Rannaud, “From the bitstream to the netlist,” in FPGA, 2008, vol. 8, pp. 264- 264.

[24] M. Tehranipoor and F. Koushanfar, “A survey of hardware trojan taxonomy and detection,” IEEE design & test of computers, vol. 27, no. 1, 2010.

[25] U. Farooq, Z. Marrakchi, and H. Mehrez, Treebased Heterogeneous FPGA Architectures: Application Specific Exploration and Optimization. Springer Science & Business Media, 2012.

[26] C. Albrecht, “IWLS 2005 benchmarks,” in International Workshop for Logic Synthesis (IWLS): http://www. iwls. org, 2005.

[27] M. Ender, S. Ghandali, A. Moradi, and C. Paar, “The First Thorough Side-Channel Hardware Trojan,” in International Conference on the Theory and Application of Cryptology and Information Security, 2017, pp. 755-780: Springer.

[28] H. Salmani, M. Tehranipoor, and R. Karri, “On design vulnerability analysis and trust benchmarks development,” in Computer Design (ICCD), 2013 IEEE 31st International Conference on, 2013, pp. 471-474: IEEE.