Volume 12 (2020)
Volume 11 (2019)
Volume 10 (2018)
Volume 9 (2017)
Volume 8 (2016)
Volume 7 (2015)
Volume 6 (2014)
Volume 5 (2013)
Volume 4 (2012)
Volume 3 (2011)
Volume 2 (2010)
Volume 1 (2009)
1. ASIC design protection against reverse engineering during the fabrication process using automatic netlist obfuscation design flow

Sh. Zamanzadeh; A. Jahanian

Volume 8, Issue 2 , Summer and Autumn 2016, , Pages 93-104

http://dx.doi.org/10.22042/isecure.2016.8.2.1

Abstract
  Fab-less business model in semiconductor industry has led to serious concerns about trustworthy hardware. In untrusted foundries and manufacturing companies, submitted layout may be analyzed and reverse engineered to steal the information of a design or insert malicious Trojans. Understanding the netlist ...  Read More

2. Self authentication path insertion in FPGA-based design flow for tamper-resistant purpose

Sh. Zamanzadeh; A. Jahanian

Volume 8, Issue 1 , Winter and Spring 2016, , Pages 53-60

http://dx.doi.org/10.22042/isecure.2016.8.1.3

Abstract
  FPGA platforms have been widely used in many modern digital applications due to their low prototyping cost, short time-to-market and flexibility. Field-programmability of FPGA bitstream has made it as a flexible and easy-to-use platform. However, access to bitstream degraded the security of FPGA IPs ...  Read More