Volume 13 (2021)
Volume 12 (2020)
Volume 11 (2019)
Volume 10 (2018)
Volume 9 (2017)
Volume 8 (2016)
Volume 7 (2015)
Volume 6 (2014)
Volume 5 (2013)
Volume 4 (2012)
Volume 3 (2011)
Volume 2 (2010)
Volume 1 (2009)
1. ASIC design protection against reverse engineering during the fabrication process using automatic netlist obfuscation design flow

Sh. Zamanzadeh; A. Jahanian

Volume 8, Issue 2 , Summer and Autumn 2016, , Pages 93-104


  Fab-less business model in semiconductor industry has led to serious concerns about trustworthy hardware. In untrusted foundries and manufacturing companies, submitted layout may be analyzed and reverse engineered to steal the information of a design or insert malicious Trojans. Understanding the netlist ...  Read More

2. Self authentication path insertion in FPGA-based design flow for tamper-resistant purpose

Sh. Zamanzadeh; A. Jahanian

Volume 8, Issue 1 , Winter and Spring 2016, , Pages 53-60


  FPGA platforms have been widely used in many modern digital applications due to their low prototyping cost, short time-to-market and flexibility. Field-programmability of FPGA bitstream has made it as a flexible and easy-to-use platform. However, access to bitstream degraded the security of FPGA IPs ...  Read More

3. Security-aware register placement to hinder malicious hardware updating and improve Trojan detectability

M. Vosoughi; A. Jahanian

Volume 7, Issue 1 , Winter and Spring 2015, , Pages 75-81


  Nowadays, bulk of the designers prefer to outsource some parts of their design and fabrication process to the third-part companies due to the reliability problems, manufacturing cost and time-to-market limitations. In this situation, there are a lot of opportunities for malicious alterations by the off-shore ...  Read More